Model inversion in integrated circuit devices having analog inference capability

A method, comprising:

• programming, in a first mode, threshold voltages of first memory cells in a first region of a memory cell array to store a first copy of weight data;
• programming, in the first mode, threshold voltages of second memory cells in a second region of the memory cell array to store second copy of weight data, wherein at least a second portion of weight bits stored in the second region is an inverted version of a first portion of weight bits stored in the first region;
• operating the first region and the second region in parallel to perform operations of multiplication and accumulation;
• generating, from the operations of multiplication and accumulation performed, a first result and a second result using the first region and the second region respectively;
• adjusting, by a logic circuit in generation of the second result, a computation result of multiplication and accumulation generated using the second region to account for weight inversion in the second portion of weight bits stored in the second region;
• and
• generating, by the logic circuit, an output result from the first result and the second result.

An apparatus, comprising:

• an integrated circuit die having a memory cell array configured in a plurality of layers, a first subset of the layers configured to store first weight matrices of an artificial neural network, and a second subset of the layers configured to store second weight matrices inverted from the first weight matrices;
• and
• an integrated circuit die having a logic circuit configured to use the first subset of the layers and the second subset of the layers concurrently to perform computations of the artificial neural network to generate a first result and a second result respectively;
• wherein the logic circuit is further configured to generate an output result of the artificial neural network based on the first result and the second result.