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US 12,190,990 B2Granted
Deferred fractional memory row activation
AssigneeRambus Inc.
InventorsJames E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
Life of this patent
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Abstract
Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
Claims20
A method of operation within a memory control component, the method comprising:
- outputting a first command/address value to a dynamic random access memory (DRAM) component during a first interval, the first command/address value including a row address and a row command, the row command instructing the DRAM component to activate a first global word line that (i) is specified by the row address and (ii) corresponds to a first row of DRAM cells within the DRAM component;
- and
- outputting a second command/address value to the DRAM component during a second interval, the second command/address value including a first sub-row address, a first column address and a first column command, the first column command instructing the DRAM component to activate a first sub-row word line that (i) is specified by the first sub-row address, (ii) corresponds to a first sub-row of DRAM cells within the first row of DRAM cells, and (iii) enables conduction, when activated, of contents of the first sub-row of DRAM cells to a first sub-row region of a sense amplifier bank within the DRAM component.
A memory control component comprising:
- a first signaling interface;
- and
- control circuitry to output to a dynamic random access memory (DRAM) component via the first signaling interface:
- a first command/address value during a first interval, the first command/address value including a row address and a row command, the row command instructing the DRAM component to activate a first global word line that (i) is specified by the row address and (ii) corresponds to a first row of DRAM cells within the DRAM component;
- and
- a second command/address value during a second interval, the second command/address value including a first sub-row address, a first column address and a first column command, the first column command instructing the DRAM component to activate a first sub-row word line that (i) is specified by the first sub-row address, (ii) corresponds to a first sub-row of DRAM cells within the first row of DRAM cells, and (iii) enables conduction, when activated, of contents of the first sub-row of DRAM cells to a first sub-row region of a sense amplifier bank within the DRAM component.
3 more elements
A memory control component comprising:
- a first signaling interface;
- and
- means for outputting to a dynamic random access memory (DRAM) component via the first signaling interface:
- a first command/address value during a first interval, the first command/address value including a row address and a row command, the row command instructing the DRAM component to activate a first global word line that (i) is specified by the row address and (ii) corresponds to a first row of DRAM cells within the DRAM component;
- and
- a second command/address value during a second interval, the second command/address value including a first sub-row address, a first column address and a first column command, the first column command instructing the DRAM component to activate a first sub-row word line that (i) is specified by the first sub-row address, (ii) corresponds to a first sub-row of DRAM cells within the first row of DRAM cells, and (iii) enables conduction, when activated, of contents of the first sub-row of DRAM cells to a first sub-row region of a sense amplifier bank within the DRAM component.
3 more elements
Dependencies are inferred from the claim text.