Method for configuring multiple input-output channels
AssigneeMicron Technology, Inc.
InventorsDean E. Walker, Tony Brewer
Life of this patent
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Abstract
A method includes setting an order of input-output channels of a column of a first chiplet of multiple chiplets of a chiplet-based system, wherein one or more of the multiple chiplets include field-configurable input-output channels arranged at a periphery of the chiplets; and programming a second chiplet of the multiple chiplets to change an order of input-output channels of a column of the second chiplet to match the order of input-output channels of the column of the first chiplet.
Claims18
A method comprising:
- setting an order of input-output channels of a column of a first chiplet of multiple chiplets of a chiplet-based system, wherein one or more of the multiple chiplets include field-configurable input-output channels arranged at a periphery of the chiplets;
- and
- programming a second chiplet of the multiple chiplets to change an order of input-output channels of a column of the second chiplet to match the order of input-output channels of the column of the first chiplet, including:
- reading a column capability register of a column of the second chiplet to determine if the order of the input-output channels of the column is reversable;
- and
- writing a column configuration register of the column of the second chiplet to reverse the order of the input-output channels of the column.
A non-transitory machine-readable medium including instructions that, when executed by a system, cause the system to perform operations comprising:
- setting an order of channels of a column of a first chiplet of multiple chiplets of the system, wherein one or more chiplets of the multiple chiplets include input-output channels arranged as one or more columns at a periphery of the chiplets;
- writing a value to a channel configuration register of the first chiplet to bond channels of the column of the first chiplet into a combined channel of the first chiplet;
- and
- writing a value to a column configuration register of a second chiplet of the multiple chiplets to reverse an order of channels of a column of the second chiplet to match the order of channels of the column of the first chiplet, and to bond one or more reversed order channels of the column of the second chiplet into a combined channel of the second chiplet to form an interface with the combined channel of the first chiplet.
Dependencies are inferred from the claim text.