Sense amplifier for coupling effect reduction

A device, comprising:

• a first input transistor having a first input and a first drain/source path;
• a second input transistor having a second input and a second drain/source path;
• a latch circuit including:
• a first latch transistor having a third drain/source path connected to the first drain/source path;
• a second latch transistor having a fourth drain/source path connected to the second drain/source path;
• a third latch transistor having a fifth drain/source path connected to the third drain/source path and to one of power and a reference;
• and
• a fourth latch transistor having a sixth drain/source path connected to the fourth drain/source path and to one of the power and the reference;
• a first transistor capacitor having a drain and a source connected at a first terminal and a gate at a second terminal, wherein the first terminal is connected to one of the first input and the fourth drain/source path and the second terminal is connected to the other one of the first input and the fourth drain/source path;
• and
• a first polycrystalline silicon on oxide diffusion edge gate to metal over diffusion capacitor including:
• a first polycrystalline silicon on oxide diffusion edge connected to a first metal layer line;
• and
• a second metal over diffusion layer connected to a second metal layer line,
• wherein the first metal layer line is connected to one of the first input and the fourth drain/source path and the second metal layer line is connected to the other one of the first input and the fourth drain/source path.

A method of operating a sense amplifier, comprising:

• applying a first voltage to a first gate of a first input transistor that has a first drain/source;
• applying a second voltage to a second gate of a second input transistor that has a second drain/source;
• comparing the first voltage on the first gate to the second voltage on the second gate, such that one of the first input transistor and the second input transistor is biased on more than another one of the first input transistor and the second input transistor;
• and
• providing a first positive feedback voltage from the second drain/source to the first gate through:
• a first metal over diffusion to metal over diffusion capacitor including:
• a first metal over diffusion layer connected to a first metal layer line;
• and
• a second metal over diffusion layer connected to a second metal layer line;
• and
• a polycrystalline silicon gate to polycrystalline silicon gate capacitor including:
• a first polycrystalline silicon gate connected to the first metal layer line;
• and
• a second polycrystalline silicon gate connected to the second metal layer line, wherein the first metal layer line is connected to one of the first gate and the second drain/source and the second metal layer line is connected to the other one of the first gate and the second drain/source.