Memory and operation method thereof

A memory comprising:

• first to Nth register circuits each configured to receive and store a failure address transferred from a memory controller when a corresponding selection signal of first to Nth selection signals is activated, where N is an integer equal to or greater than 2;
• first to Nth resource latch circuits configured to store first to Nth resource signals indicating availability of the first to Nth register circuits, respectively;
• and
• a priority selection circuit configured to activate, when two or more of the first to Nth resource signals are activated, a high priority selection signal of selection signals respectively corresponding to the activated resource signals among the first to Nth selection signals,
• wherein the high priority selection signal activates one register circuit having a high priority among the first to Nth register circuits.