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US 12,190,981 B2Granted
Memory array having error checking and correction circuit
AssigneeWinbond Electronics Corp.
InventorsYao-Ting Tsai, Che-Fu Chuang
Life of this patent
Estimating the term…
Abstract
A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.
Claims18
A memory array comprising:
- a repeating unit comprising:
- a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of data storage regions;
- and
- a plurality of groups of word lines extending across one of the plurality of memory blocks and being connected to a plurality of overlying signal lines through a plurality of groups of first word line contact regions in the plurality of memory blocks and a plurality of second word line contact regions between the plurality of memory blocks,
- wherein a peripheral memory block in the plurality of memory blocks further comprises an error checking and correction circuit region, and an error checking and correction circuit in the error checking and correction circuit region is configured to perform error checking and correction for the plurality of data storage regions of each of the plurality of memory blocks in the repeating unit.
2 more elements
A memory array comprising:
- a plurality of memory blocks defined by a plurality of wells, wherein the plurality of wells are disposed in a substrate and arranged in parallel, and each of the memory blocks comprises a plurality of data storage regions;
- and
- a plurality of well taps located on the substrate, extending along a single outer contour surrounding the plurality of wells, and electrically connected to the plurality of wells,
- wherein the plurality of well taps comprise:
- two first well taps respectively surrounding two peripheral wells in the plurality of wells on three sides;
- and
- a plurality of second well taps each having two line segments separated from each other, the plurality of second well taps extending along opposite sides of a plurality of central wells in the plurality of wells.
4 more elements
Dependencies are inferred from the claim text.