Semiconductor memory apparatus and testing method thereof

A semiconductor memory apparatus, comprising:

• a memory chip comprising a main array and a mini array;
• and
• a memory controller coupled to the memory chip and configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in the main array,
• wherein after the memory chip is idle for a first time, the memory controller applies a read voltage to the target memory cell to detect a first test voltage of the target memory cell according to a first read current generated from the target memory cell and compares the first test voltage with a current comparison voltage to determine whether a first stage test is passed,
• in a case of passing the first stage test, after the memory chip is idle for a second time, the memory controller applies the read voltage to the target memory cell to detect a second test voltage of the target memory cell according to a second read current generated from the target memory cell and compares the second test voltage with the current comparison voltage to determine whether a second stage test is passed, and the current comparison voltage is dynamically updated in response to a time the memory chip is idle.