Dynamic random access memory built-in self-test power fail mitigation

A system comprising:

• a dynamic random access memory (DRAM) device, comprising:
• one or more mode registers, each mode register having a plurality of bits;
• a memory array;
• Memory Built-in Self Test circuitry to use patterns to test the memory array, the Memory Built-in Self Test circuitry to store a status of the test of the memory array in a first mode register;
• and
• repair circuitry to perform a hard repair of a first portion of faulty memory cells in the memory array detected by the Memory Built-in Self Test circuitry, the first portion of faulty memory cells capable of repair during a repair time,
• a display communicatively coupled to a processor to display data stored in the DRAM device.

A method comprising:

• testing, by Memory Built-in Self Test circuitry in a synchronous dynamic random access memory (SDRAM) device, a memory array in the DRAM using test patterns;
• storing status of the testing of the memory array in a first mode register of a plurality of mode registers in the SDRAM device, each mode register having a plurality of bits;
• and
• performing, by repair circuitry in the SDRAM device, a hard repair of a first portion of faulty memory cells in the memory array detected by the Memory Built-in Self Test circuitry, the first portion of faulty memory cells capable of repair during a repair time.