DRAM retention test method for dynamic error correction
AssigneeRambus Inc.
InventorsEly Tsern, Frederick A Ware, Suresh Rajan, Thomas Vogelsang
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Abstract
A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.
Claims20
An integrated circuit (IC) dynamic random access memory (DRAM) memory controller comprising:
- a storage interface to access storage, the storage to store row address information of storage cells that are associated with a detected error;
- test circuitry to perform test operations on an array of DRAM storage cells, the array of DRAM storage cells organized into multiple rows that are accessible via corresponding row addresses, each of the multiple rows including multiple columns of DRAM storage cells that are accessible via corresponding column addresses, the test circuitry operable to
- perform consecutive access operations to access column data corresponding to each of the multiple columns of each of the multiple rows;
- for each of the consecutive access operations, determine whether the accessed column data includes at least one error;
- and
- if at least one error is detected in the accessed column data,
- correct the at least one error, and
- update the storage to include the corresponding row address of the detected column data that included the at least one error.
A method of operation in an integrated circuit (IC) dynamic random access memory (DRAM) memory controller, the method comprising:
- performing test operations on an array of DRAM storage cells, the array of DRAM storage cells organized into multiple rows that are accessible via corresponding row addresses, each row address including multiple columns that are accessible via corresponding column addresses, the test operations including
- performing consecutive access operations to access column data corresponding to each of the multiple columns of each of the multiple rows;
- for each of the consecutive access operations, determining whether the accessed column data includes at least one error;
- and
- if at least one error is detected in the accessed column data,
- correcting the at least one error, and
- storing the corresponding row address of the detected column data that included the at least one error, the storing carried out with off-chip storage.
An integrated circuit (IC) dynamic random access memory (DRAM) memory controller comprising:
- a storage interface to access storage, the storage to store row address information of storage cells that are associated with a detected error;
- test circuitry including
- a test counter to generate consecutive column addresses to access corresponding columns of DRAm storage cells;
- error detection circuitry, for each generated column address, to determine whether column data stored in the column storage cells corresponding to the column address includes at least one error;
- and
- error correction circuitry, if at least one error is detected, to correct the at least one error, and
- circuitry to update the storage to include a corresponding row address of the detected column data that included the at least one error.
Dependencies are inferred from the claim text.