Power control device and power test system

A power test system, wherein the system comprises a memory and a processor, a plurality of instructions executed by the processor are stored in the memory, and the processor is configured to:

• obtain at least one power-supply path manner of at least one power-down test device;
• determine at least one power-supply path interface according to the at least one power-supply path manner;
• determine at least one electronic switch according to the at least one power-supply path interface, wherein the at least one electronic switch is used to control a change of electrical energy;
• determine at least one target device to be tested;
• obtain device information of the at least one target device;
• match the device information with a power-down test table to obtain at least one power-down test instruction, wherein the power-down test table stores a mapping relationship between the device information and the at least one power-down test instruction;
• wherein the power-down test table is pre-established, each of the at least one power-down test instruction includes a power-supply path establishment parameter and a power-down execution parameter;
• establish, according to the power-supply path establishment parameter, a target power-supply path corresponding to the at least one target device between the at least one power-supply path interface and the at least one electronic switch;
• and
• on the target power-supply path, perform a power-down operation according to the power-down execution parameter to perform a power-down test on the at least one target device.