Erase suspend with configurable forward progress
AssigneeMicron Technology, Inc.
InventorPhil Reusswig
Life of this patent
Estimating the term…
Abstract
Aspects of the present disclosure configure a memory sub-system processor to manage memory erase operations. The processor accesses a configuration register to identify a quantity of memory slices to erase. The processor divides a set of memory components into a plurality of portions based on the identified quantity of memory slices to erase and performs one or more read operations in association with the memory sub-system between erasure of each of the plurality of portions of the set of memory components.
Claims20
A system comprising:
- a set of memory components of a memory sub-system;
- and
- a processing device operatively coupled to the set of memory components, the processing device being configured to perform operations comprising:
- accessing a configuration register to identify a quantity of memory slices to erase;
- dividing the set of memory components into a plurality of portions based on the identified quantity of memory slices to erase;
- and
- performing one or more read operations in association with the memory sub-system between erasure of each of the plurality of portions of the set of memory components.
A computerized method comprising:
- accessing a configuration register to identify a quantity of memory slices to erase;
- dividing a set of memory components into a plurality of portions based on the identified quantity of memory slices to erase;
- and
- performing one or more read operations in association with a memory sub-system between erasure of each of the plurality of portions of the set of memory components.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- accessing a configuration register to identify a quantity of memory slices to erase;
- dividing a set of memory components into a plurality of portions based on the identified quantity of memory slices to erase;
- and
- performing one or more read operations in association with a memory sub-system between erasure of each of the plurality of portions of the set of memory components.
Dependencies are inferred from the claim text.