Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell

An apparatus comprising:

• a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node;
• a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias;
• a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line;
• and
• one or more circuitries to perform a first read operation during a first phase on a selected capacitor of the plurality of capacitors, wherein the one or more circuitries is to perform a second read operation during a second phase, wherein the second read operation mitigates read disturb effects on unselected capacitors of the plurality of capacitors, wherein the one or more circuitries is to ramp a voltage on a plate-line coupled to the selected capacitor in a staircase fashion to a supply voltage level during the first phase, wherein the one or more circuitries is to set the voltage on the plate-line of the selected capacitor to a ground voltage level in the second phase, and wherein the one or more circuitries is to set the bit-line to a high-impedance state during a time when the voltage on the plate-line of the selected capacitor is between the supply voltage level and the ground voltage level.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a memory circuitry to store the one or more instructions;
• and
• a communication interface to allow the processor circuitry to communicate with another device, wherein the memory circuitry includes a plurality of bit-cells organized in a memory array, and wherein an individual bit-cell of the plurality of bit-cells includes:
• a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node;
• a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line;
• and
• one or more circuitries to perform a first read operation during a first phase on a selected capacitor of the plurality of capacitors, wherein the one or more circuitries is to perform a second read operation during a second phase, wherein the second read operation mitigates read disturb effects on unselected capacitors of the plurality of capacitors, wherein the one or more circuitries is to ramp a voltage on a plate-line coupled to the selected capacitor in a staircase fashion to a supply voltage level during the first phase, wherein the one or more circuitries is to set the voltage on the plate-line of the selected capacitor to a ground voltage level in the second phase, and wherein the one or more circuitries is to set voltages on plate-lines coupled to the unselected capacitors to be between the supply voltage level and the ground voltage level during the first phase and the second phase.