SRAM power-up random number generator

A method, comprising:

• applying a first voltage level to a memory cell array, the memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines;
• initiating a word line glitch;
• generating a random number based on an initial state of each of the plurality of bit cells in response to the word line glitch;
• receiving a shutdown signal;
• and
• in response to the shutdown signal, applying the first voltage level to the memory cell array.

A method, comprising:

• receiving a shutdown signal;
• in response to the shutdown signal, applying a first voltage level to a memory array, the memory cell array having a plurality of bit cells coupled to a plurality of bit lines and a plurality of word lines;
• precharging the bit lines to a second voltage level lower than the first voltage level during a random number generator (RNG) phase;
• determining an initial state of the bit cells during the RNG phase;
• and
• powering the memory cell array up and down a predetermined number of cycles before receiving the shutdown signal.