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US 12,190,944 B2Granted
Memory device with signal edge sharpener circuitry
AssigneeTaiwain Semiconductor Manufacturing Company, Ltd.
InventorAtul Katoch
Life of this patent
Estimating the term…
Abstract
Signal edge sharpener circuitry is operably connected to the word lines in a memory array to pull up a rising edge of a signal on the word line and/or to pull down a falling edge of the signal on the word line. Pulling the signal up and/or down reduces the amount of time the word line is asserted and reduces the amount of time between precharge operations.
Claims20
A method, comprising:
- transmitting a clock signal to a row driver circuit and to a delay circuit:
- deactivating a word line based on the clock signal received by the row driver circuit, the word line operably connected to a memory cell;
- transmitting a delayed clock signal output by the delay circuit to a control terminal of signal edge sharpener circuitry operably connected to a distal end of the word line;
- based on the delayed clock signal, causing, by the signal edge sharpener circuitry, a rising edge of a word line signal on the word line to be pulled up at an increased rate;
- and
- initiating a precharge operation on a bit line in response to the rising edge of the word line signal on the word line being pulled up to a predetermined level.
3 more elements
A memory device, comprising:
- a memory cell;
- a word line operably connected to the memory cell;
- a delay circuit configured to receive a clock signal and to output a delayed clock signal;
- and
- signal edge sharpener circuitry operably connected to a distal end of the word line and to the delay circuit, the signal edge sharpener circuitry having a control terminal configured to receive the delayed clock signal from the delay circuit and responsively pull up a rising edge of a word line signal on the word line at an increased rate.
2 more elements
A system, comprising:
- a processing device;
- and
- a memory device operably connected to the processing device, the memory device comprising:
- a memory cell;
- a word line operably connected to the memory cell, wherein a proximate end of the word line is operably connected to row driver circuitry;
- a delay circuit configured to receive a clock signal and output a delayed clock signal;
- signal edge sharpener circuitry operably connected between a distal end of the word line and an output of the delay circuit, the signal edge sharpener circuitry having a control terminal configured to receive the delayed clock signal and responsively pull up a rising edge of a word line signal on the word line at an increased rate;
- and
- a load circuit operably connected to the output of the delay circuit.
6 more elements
Dependencies are inferred from the claim text.