Memory cell and memory device thereof

A memory device including:

• a memory array including a plurality of memory cells, a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines and a plurality of fourth signal lines, the memory cells coupled to the first, the second, the third and the fourth signal lines;
• a plurality of driving circuits coupled to the memory array, for applying a plurality of driving voltages to the memory cells via the first, the second, the third and the fourth signal lines to write or read the memory cells;
• and
• a plurality of sensing amplifiers coupled to the memory array, for sensing a plurality of read currents from the memory cells,
• wherein each of the memory cells comprising:
• a write transistor;
• and
• a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data;
• wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable, and the storage node is connected to a control terminal of the read transistor.