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US 12,190,937 B2Granted
Anti-row-hammer memory device
AssigneeSamsung Electronics Co., Ltd.
InventorByoung Kon Jo
Life of this patent
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Abstract
A memory device is provided that comprises: a memory cell array having a plurality of memory cells connected between a plurality of word lines and a plurality of column lines; a three-phase word line controller configured to generate a selected operating voltage, a first unselected operating voltage, and a second unselected operating voltage having a lower level than the first unselected operating voltage; and a row decoder connected to the plurality of word lines, configured to apply the selected operating voltage to an activated word line on the basis of a row address, and to apply the first unselected operating voltage or the second unselected operating voltage to a deactivated word line.
Claims20
A memory device comprising:
- a memory cell array having a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines;
- a row decoder circuit connected to the plurality of word lines, and configured to select a first word line among the plurality of word lines based on a row address;
- an active counter circuit configured to generate a control signal based on comparing a number of accesses to the first word line with a preset threshold value;
- a three-phase word line controller configured to determine an operation mode of the sub word line driver circuit based on the control signal;
- and
- a sub word line driver circuit configured to:
- in a row-hammer protection mode, apply a selected operating voltage to the first word line, and apply a first unselected operating voltage to a second word line among the plurality of word lines, which is different from the first word line;
- and
- in a normal mode, apply the selected operating voltage to the first word line, and apply a second unselected operating voltage to the second word line, wherein the second unselected operating voltage has a voltage level that is lower than the first unselected operating voltage.
6 more elements
A memory device comprising:
- a plurality of memory cell regions connected to a plurality of word lines and bit lines and disposed in a slave layer;
- a voltage generator disposed on a master layer, and configured to generate a selected operating voltage, a first unselected operating voltage, and a second unselected operating voltage having a level lower than the first unselected operating voltage;
- a plurality of sub-word line drivers disposed on the slave layer and connected to the plurality of word lines, and configured to apply an operating voltage to the word line;
- and
- an active counter disposed on the master layer, and configured to generate a control signal based on comparing a number of accesses to one the plurality of word lines and a predetermined threshold value;
- and
- a three-phase word line controller disposed in the slave layer, and configured to control the plurality of sub-word line drivers to apply the selected operating voltage to a first word line among the plurality of word lines selected on the basis of a row address, apply the second unselected operating voltage to a second word line among the plurality of word lines that is adjacent to the first word line, and apply the first unselected operating voltage to a third word line among the plurality of word lines that is not adjacent to the first word line based on the control signal.
4 more elements
A memory device comprising:
- a plurality of memory cell regions disposed on a plurality of word lines and a plurality of bit lines;
- an active counter configured to generate a control signal based on comparing a number of accesses to one the plurality of word lines and a predetermined threshold value;
- and
- a plurality of sub word line drivers including a first sub word line driver, a second sub word line driver and a third sub word line driver, each of the plurality of sub word line drivers comprising:
- a PMOS transistor which is connected to a word line activation address line at one side, and configure to output a selected operating voltage;
- a first NMOS transistor which is connected to a first power voltage line different from the word line activation address line at one side, and configured to output a first unselected operating voltage;
- a second NMOS transistor which is connected to a second power voltage line different from the first power voltage line at one side, and configured to output a second unselected operating voltage lower than the first unselected operating voltage;
- a three-phase word line controller configured to control the plurality of sub word line driver based on the control signal;
- a first sub-word line driver configured to apply the selected operating voltage to the first word line on the basis of a row address;
- a second sub-word line driver configured to apply the second unselected operating voltage to a second word line adjacent to the first word line;
- and
- a third sub-word line driver configured to apply the first unselected operating voltage to a third word line adjacent to the second word line in a direction opposite to the first word line.
9 more elements
Dependencies are inferred from the claim text.