Memory and operation method thereof
AssigneeSK hynix Inc.
InventorSang Woo Yoon
Life of this patent
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Abstract
An operation method of a memory may include receiving an active command and an active address; determining whether a row corresponding to the active address and a row corresponding to a target row address are able to be substantially simultaneously activated; activating the row corresponding to the active address; and activating the row corresponding to the target row address in response to determining that the row corresponding to the active address and the row corresponding to the target row address are able to be substantially simultaneously activated.
Claims12
An operation method of a memory, the operation method comprising:
- receiving an active command and an active address;
- determining whether a row corresponding to the active address and a row corresponding to a target row address share a bit line sense amplifier;
- activating the row corresponding to the active address;
- and
- activating the row corresponding to the target row address when the row corresponding to the active address and the row corresponding to the target row address are determined to share the bit line sense amplifier.
A memory comprising:
- a target row refresh operation control circuit configured to determine whether to perform a target row refresh operation during an active operation by determining whether a row corresponding to an active address and a target row corresponding to a target row address share a bit line sense amplifier;
- a target row collection circuit configured to collect the target row address;
- and
- a memory core including memory cells arranged in a plurality of rows and a plurality of columns and configured to activate the row corresponding to the active address and the target row corresponding to the target row address when it is determined to perform the target row refresh operation during the active operation.
Dependencies are inferred from the claim text.