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US 12,190,934 B2Granted
Memory with row hammer mitigation technique
AssigneeSK hynix Inc.
InventorsWoongrae Kim, Hoiju Chung
Life of this patent
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Abstract
A memory includes: a memory core; a list storage circuit suitable for storing a weak row list of rows that are vulnerable to a row hammer attack in the memory core; and a row hammer attack detection circuit suitable for selecting rows that are row-hammer-attacked among rows in the memory core as hammered rows, and increasing a probability that the rows stored in the list storage circuit are selected as the hammered rows.
Claims9
A memory comprising:
- a memory core;
- a list storage circuit suitable for storing a weak row list that includes a list of rows that have been determined to be more vulnerable to a row hammer attack and data loss, as compared to other rows in the memory core also row hammered attacked, wherein the rows more vulnerable to the row hammer attack are divided into multiple levels according to a degree of vulnerability;
- and
- a row hammer attack detection circuit suitable for selecting rows that are row-hammer-attacked among rows in the memory core as hammered rows,
- wherein the row hammer attack detection circuit increases a probability that the rows in the list of rows that have been determined to be more vulnerable to a row hammer attack and data loss in the list storage circuit are selected as the hammered rows.
2 more elements
A memory comprising:
- a memory core;
- a list storage circuit suitable for storing a weak row list that includes a list of rows that have been determined to be more vulnerable to a row hammer attack and data loss, as compared to other rows in the memory core also row hammered attacked, wherein the rows more vulnerable to the row hammer attack are divided into multiple levels according to a degree of vulnerability;
- a sampling circuit suitable for sampling and storing a portion of active addresses used for active operations of the memory core and increasing a sampling probability of an active address corresponding to the rows stored in the list storage circuit among the active addresses;
- and
- a selection circuit suitable for selecting one among the sampled addresses stored in the sampling circuit as a hammered row address in a predetermined order whenever a smart refresh operation is performed,
- wherein the selection circuit selects, when there is an address corresponding to a row stored in the list storage circuit among the sampled addresses, the row address as a hammered row address, and
- wherein the selection circuit increases a probability that the rows in the list of rows that have been determined to be more vulnerable to a row hammer attack and data loss in the list storage circuit are selected as the hammered rows.
4 more elements
A memory comprising:
- a memory core;
- a list storage circuit suitable for storing a weak row list of rows that are determined to be more vulnerable to a row hammer attack, as compared to the other rows in the memory core, wherein the rows more vulnerable to the row hammer attack are divided into multiple levels according to a degree of vulnerability;
- and
- a row hammer attack detection circuit suitable for selecting rows that are row-hammer-attacked among rows in the memory core as hammered rows and increasing a probability that the rows stored in the list storage circuit are selected as the hammered rows,
- wherein the row hammer attack detection circuit samples the other rows, except the rows stored in the list storage circuit, with a low probability when an active operation is performed while the rows stored in the list storage circuit are sampled with a high probability.
2 more elements
Dependencies are inferred from the claim text.