US 12,190,930 B2 · Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells

Abstract

Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

Claims20

Dependent claims

A structure comprising:

a multiplexing circuit including:
multiple data line inputs;
multiple select line inputs;
and a multiplexing circuit output node;
and
multiple memory cells, wherein each memory cell includes:
a first transistor;
a second transistor, wherein the second transistor has an electric field-based programmable threshold voltage and wherein the first transistor and the second transistor are connected in series between a first voltage source line and a second voltage source line;
a sense node at a junction between the first transistor and the second transistor;
a memory cell output node;
a first inverter;
and
a second inverter, wherein the first inverter and the second inverter are connected in series between the sense node and the memory cell output node and wherein the memory cell output node is connected to one of the data line inputs of the multiplexing circuit.

10 more elements

A structure comprising:

a multiplexing circuit including:
multiple data line inputs;
multiple select line inputs;
and a multiplexing circuit output node;
and
multiple memory cells, wherein each memory cell includes:
a first transistor;
a second transistor, wherein the second transistor has an electric field-based programmable threshold voltage, wherein the first transistor and the second transistor are connected in series between a first voltage source line and a second voltage source line, and wherein the first transistor has a first gate connected to a first wordline and the second transistor has a second gate connected to a second wordline;
a sense node at a junction between the first transistor and the second transistor;
a memory cell output node;
a first inverter;
and
a second inverter, wherein the first inverter and the second inverter are connected in series between the sense node and the memory cell output node and wherein the memory cell output node is connected to one of the data line inputs of the multiplexing circuit.

10 more elements

Dependencies are inferred from the claim text.

Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells

Life of this patent

Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells

Life of this patent

Abstract

Claims20