Memory device with a bias circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng Chang, Chia-En Huang, Gu-Huan Li
Life of this patent
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Abstract
A method for operating a memory device is provided. A first address is decoded to select a bit line of a memory device. A second address is decoded to select a word line of the memory device. A word line voltage is applied to the selected word line. A bit line voltage is applied to the selected bit line. A first bias voltage is applied to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line san a memory cell connected to both the selected bit line and the selected word line.
Claims20
A method for operating a memory device, the method comprising:
- decoding a first address to select a bit line of a memory device;
- decoding a second address to select a word line of the memory device;
- applying a word line voltage to the selected word line;
- applying a bit line voltage to the selected bit line;
- applying a first bias voltage to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line except a memory cell connected to both the selected bit line and the selected word line, the first bias voltage being different than the word line voltage applied to the selected word line, wherein applying the first bias voltage comprises applying the first bias voltage that is less than 0 volt;
- and
- applying a second bias voltage to a gate of a reference memory cell transistor of a reference circuit, wherein the second bias voltage is greater than a supply voltage of the memory device.
A method of performing a read operation in a memory device, the method comprising:
- applying a word line voltage to a selected word line of a memory device;
- applying a bit line voltage to a selected bit line of the memory device;
- applying a first bias voltage to each of a plurality of unselected word lines connected a plurality of memory cells connected to the selected bit line except a memory cell connected to both the selected word line and the selected bit line, the first bias voltage being different than the word line voltage applied to the selected word line, wherein applying the first bias voltage comprises applying the first bias voltage that is less than 0 volt;
- applying a second bias voltage to a gate of a reference memory cell transistor of a reference circuit, wherein the second bias voltage is greater than a supply voltage of the memory device;
- and
- comparing a reference current generated by the reference circuit and a read current flowing through the memory device.
A memory device comprising:
- a word line decoder connected to a memory cell array, wherein the word line decoder selects a word line of the memory cell array;
- a bit line decoder connected to the memory cell array, wherein the bit line decoder selects a bit line of the memory cell array;
- a reference circuit to generate a reference current;
- a sense amplifier connected to the reference circuit and the memory cell array, wherein the sense amplifier compares a read current flowing to the memory cell array and the reference current;
- and
- a bias circuit configured to:
- apply a first bias voltage to a to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line except a memory cell connected to both the selected word line and the selected bit line, the first bias voltage being different than a word line voltage applied to the selected word line, wherein applying the first bias voltage comprises applying the first bias voltage that is less than 0 volt, and
- apply a second bias voltage to a gate of a reference memory cell transistor of the reference circuit, wherein the second bias voltage is greater than a supply voltage of the memory device.
Dependencies are inferred from the claim text.