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US 12,190,826 B2Granted
Gate driving circuit
AssigneeSamsung Display Co., Ltd.
InventorsYoungwan Seo, Haemin Kim, Geunho Lee
Life of this patent
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Abstract
A gate driving circuit from which stable gate signals may be output by minimizing a leakage current of turned-off transistors in case that pull-down transistors output a gate signal and a carry signal of a low-level voltage. Some transistors in the gate driving circuit include two transistors in series to reduce leakage current in an off state, and capacitors are further included to reduce leakage current. Therefore voltages at nodes can be better controlled, and so that the output gate and carry voltages can be stably controlled.
Claims20
A gate driving circuit comprising:
- a plurality of stages, each comprising:
- a node controller that controls voltage levels of a first node and a second node;
- a first output portion that outputs a gate signal having a voltage of a first level or a voltage of a second level lower than the first level according to the voltage levels of the first node and the second node;
- a second output portion that outputs a carry output signal having the voltage of the first level or a voltage of a third level lower than the second level according to the voltage levels of the first node and the second node, wherein
- the node controller comprises:
- a first stabilization transistor and a second stabilization transistor electrically connected in series between the first node and a voltage input terminal to which the voltage of the third level is applied;
- and
- a first capacitor electrically connected between the first stabilization transistor and the second stabilization transistor,
- the first stabilization transistor is electrically connected between the first node and the first capacitor and including a gate electrically connected to a first clock input terminal to which a first clock signal is applied, and
- the second stabilization transistor is electrically connected between the first capacitor and the voltage input terminal to which the voltage of the third level is applied and including a gate electrically connected to the second node.
7 more elements
A gate driving circuit comprising:
- a plurality of stages, each comprising:
- a node controller that controls voltage levels of a first node and a second node;
- a first output portion that outputs a gate signal having a voltage of a first level or a voltage of a second level lower than the first level to a first output terminal according to the voltage levels of the first node and the second node;
- and
- a second output portion that outputs a carry output signal having the voltage of the first level or a voltage of a third level lower than the second level to a second output terminal according to the voltage levels of the first node and the second node, wherein
- the first output portion includes a first pull-up transistor electrically connected between a first clock input terminal to which a first clock signal is applied and the first output terminal and including a gate electrically connected to the first node,
- the second output portion includes a second pull-up transistor electrically connected between the first clock input terminal and the second output terminal and including a gate electrically connected to the first node, and
- the second pull-up transistor includes a plurality of sub-transistors electrically connected in series.
5 more elements
Dependencies are inferred from the claim text.