Pixel circuit, pixel driving method and display device

A pixel circuit, comprising a first initialization circuit, a compensation circuit and a data writing-in circuit, wherein:

• the first initialization circuit is electrically connected to an initial control line, a first initial voltage terminal and a driving control node, and is configured to control the first initial voltage terminal to write a first initial voltage into the driving control node under the control of an initial control signal provided by the initial control line;
• the compensation circuit is electrically connected to a compensation control line, the driving control node and a first node, and is configured to control the driving control node to be connected to the first node under the control of a compensation control signal provided by the compensation control line;
• one of the first initialization circuit and the compensation circuit comprises a low temperature polysilicon thin film transistor and an oxide transistor connected in series, and the other of the first initialization circuit and the compensation circuit only comprises an oxide thin film transistor;
• the data writing-in circuit is electrically connected to a writing-in control line, a data line and a second node respectively, and is configured to, under the control of a writing-in control signal provided by the writing-in control line, control to write a data voltage on the data line into the second node;
• the first initialization circuit comprises a first transistor and a third transistor, the compensation circuit comprises a second transistor, and the data writing-in circuit comprises a seventh transistor;
• and the third transistor is an oxide transistor;
• wherein
• a control electrode of the third transistor is electrically connected to a first scan line in an (n−1)th row, where n is a positive integer;
• a control electrode of the first transistor is electrically connected to the initial control line;
• a control electrode of the second transistor is electrically connected to the compensation control line;
• a control electrode of the seventh transistor is electrically connected to the writing-in control line;
• the initial control line is a second scan line in the (n−1)th row, the compensation control line is a first scan line in an nth row, the writing-in control line is a second scan line in an nth row;
• the first scan line in the nth row and the first scan line in the (n−1)th row have a same waveform with a shifted phase, the second scan line in the nth row and the second scan line in the (n−1)th row have a same waveform with the shifted phase;
• and
• a display period of the pixel circuit comprises an initialization stage and a data writing-in stage that are set in sequence;
• in the initialization stage and the data writing-in stage, a turning-on period of the first transistor and the third transistor does not overlap a turning-on period of the second transistor and the seventh transistor;
• or,
• the first initialization circuit comprises a first transistor, the compensation circuit comprises a second transistor and a fourth transistor;
• and the data writing-in circuit comprises a seventh transistor;
• and the first transistor is an oxide transistor;
• wherein
• a control electrode of the first transistor is electrically connected to the initial control line;
• a control electrode of the second transistor is electrically connected to the compensation control line, and a first electrode of the second transistor is electrically connected to the driving control node;
• a control electrode of the fourth transistor is electrically connected to a first scan line in an nth row;
• where n is a positive integer;
• a first electrode of the fourth transistor is merely electrically connected to the second electrode of the second transistor, and a second electrode of the fourth transistor is electrically connected to the first node;
• a control electrode of the seventh transistor is electrically connected to the writing-in control line;
• or,
• a control electrode of the first transistor is electrically connected to the initial control line;
• a control electrode of the second transistor is electrically connected to the compensation control line, a first electrode of the second transistor is merely electrically connected to a second electrode of the fourth transistor, and a second electrode of the second transistor is electrically connected to the first node;
• a control electrode of the fourth transistor is electrically connected to a first scan line in an nth row, and a first electrode of the fourth transistor is electrically connected to the driving control node;
• a control electrode of the seventh transistor is electrically connected to the writing-in control line;
• and
• wherein the second transistor and the seventh transistor are p-type transistors, and the first transistor and the fourth transistor are n-type transistors,
• the initial control line is a first scan line in an (n−1)th row, and the compensation control line is a second scan line in the nth row;
• the writing-in control line is a second scan line in an nth row;
• the first scan line in the nth row and the first scan line in the (n−1)th row have a same waveform with a shifted phase, the second scan line in the nth row and the second scan line in the (n−1)th row have a same waveform with the shifted phase;
• and
• a display period of the pixel circuit comprises an initialization stage and a data writing-in stage that are set in sequence;
• in the initialization stage and the data writing-in stage, a turning-on period of the first transistor does not overlap a turning-on period of the second transistor, the fourth transistor and the seventh transistor.