Gate driving circuits and display panels

A display panel, comprising a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded gate driving units, wherein each gate driving unit of at least one gate driving unit of the gate driving units comprises:

• a pull-up control module configured to pull up a level of a first node of the each gate driving unit in response to a stage-transmission signal;
• a pull-up module,
• wherein a control terminal of the pull-up module is electrically connected to the pull-up control module through the first node, an input terminal of the pull-up module is electrically connected to a clock signal line to load a clock signal, an output terminal of the pull-up module is electrically connected to a gate line, and
• the pull-up module is configured to respond to the level of the first node to transmit the clock signal to the gate line;
• a pull-down maintaining module,
• wherein the pull-down maintaining module is electrically connected between the first node and a voltage line and is electrically connected to the control terminal of the pull-up module through the first node,
• the pull-down maintaining module comprises an inverter module and a switch element,
• a control terminal of the inverter module is electrically connected to the first node, and an output terminal of the inverter module is electrically connected to a control terminal of the switch element, and
• the switch element is configured to control connection between the gate line and the voltage line;
• and
• a voltage control module,
• wherein the voltage control module is electrically connected to the output terminal of the inverter module,
• the voltage control module is configured to control a first transition edge of a signal at the output terminal of the inverter module to lag behind a second transition edge of the clock signal within a duration of a corresponding clock pulse of the clock signal,
• the first transition edge is arranged adjacent to the second transition edge on a time axis, and
• the second transition edge corresponds to an end of the clock pulse.