Processing system, related integrated circuit, device and method

A method for operating a processing system comprising a Serial Peripheral Interface (SPI) communication interface and a microprocessor communicatively connected to the SPI communication interface, the method comprising:

• programming, by the microprocessor, when in a CAN FD Light data transmission mode, a control register of the SPI communication interface in order to activate a master mode;
• generating, by the microprocessor, a transmission CAN FD Light frame;
• storing, by the microprocessor, the transmission CAN FD Light frame to a memory;
• and
• activating, by the microprocessor, a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register of the SPI communication interface.

A processing system comprising:

• a Serial Peripheral Interface (SPI) communication interface;
• and
• a microprocessor communicatively connected to the SPI communication interface, wherein the microprocessor, when in a CAN FD Light data reception mode, is configured to:
• program a control register of the SPI communication interface in order to activate a slave mode;
• in response to receive a first control signal, enable a first hardware timer circuit and a second hardware timer circuit, wherein a second DMA channel is able to transfer packets of a given word size from a reception shift register to a memory thereby sequentially transferring a reception CAN FD Light frame from the reception shift register to the memory;
• and
• in response to a second control signal, read the reception CAN FD Light frame from the memory.

A method for operating a processing system comprising a Serial Peripheral Interface (SPI) communication interface and a microprocessor communicatively connected to the SPI communication interface, the method comprising:

• programming, by the microprocessor, when in a CAN FD Light data reception mode, a control register of the SPI communication interface in order to activate a slave mode;
• in response to receive a first control signal, enabling a first hardware timer circuit and a second hardware timer circuit, wherein a second DMA channel is able to transfer packets of a given word size from a reception shift register to a memory thereby sequentially transferring a reception CAN FD Light frame from the reception shift register to the memory;
• and
• in response to a second control signal, reading the reception CAN FD Light frame from the memory.