US 12,184,307 B2 · Mitigating DBI bit flip induced errors

Abstract

The present disclosure generally relates to improving data transfer in a data storage device. In double data rate (DDR) systems that include a data bus inversion (DBI) functionality, bit flip events can be more prevalent. To mitigate the effect of enhanced erroneous bit flip rate related to DBI bit flip events, the DBI bit can stay static for a predetermined number of consecutive clock cycles, the error correction module can be informed of reduced reliability due to active DBI bit events, the DBI bit can be set to 0, or combinations thereof. Setting the DBI bit to 0 effectively cancels DBI functionality. Informing the error correction module permits a more robust error correction to occur. Forcing the DBI bit to remain static reduces the probability of an unrecognized bit flip event of a full byte. In so doing, data transfer reliability is improved when using DBI functionality.

Claims15

Dependent claims

A data storage device, comprising:

a memory device;
and
a controller coupled to the memory device, wherein the controller is configured to:
receive data from a host device;
arrange the data into one or more bursts, wherein each burst comprises a plurality of bytes;
set a data bus inversion (DBI) bit for each byte, wherein a plurality of consecutive DBI bits within at least one burst of the one or more bursts are identical, and wherein the plurality of consecutive DBI bits that are identical corresponds to a predetermined number of clock cycles;
send the one or more bursts and DBI bits to the memory device;
send a first reliability indication to the memory device, wherein the first reliability indication is based on a search of a log likelihood ratio (LLR) table of the received data;
send a second reliability indication to the memory device, wherein the second reliability indication is based on a search of a DBI LLR table of the DBI bit;
and
determine a decoding level based upon the first and second reliability indicator.

8 more elements

Dependencies are inferred from the claim text.

Mitigating DBI bit flip induced errors

Life of this patent

Mitigating DBI bit flip induced errors

Life of this patent

Abstract

Claims15