US 12,184,302 B2 · Data register unit, SAR ADC and electronic device

Abstract

A data register unit, a SAR ADC and an electronic device are disclosed. The data register unit comprises: a first high-speed flip-flop; a second high-speed flip-flop; and a first logic gate, wherein the first high-speed flip-flop and the second high-speed flip-flop comprise a high-speed flip-flop circuit respectively, which comprises: a first PMOS transistor, a first NMOS transistor, an inverter and a logic gate. The data register unit of the present disclosure is composed of a high-speed flip-flop circuit with a very simple structure and suitable for fast operation. In a further embodiment, the high-speed flip-flop circuit can combine the bit pulse to realize the capacitor switching based on the comparison result. This increases the operation speed of the SAR ADC while significantly reducing the number of transistors required to implement the EMCS logic.

Claims20

Dependent claims

A data register unit comprising:

a first high-speed flip-flop;
a second high-speed flip-flop;
a first logic gate,
wherein, the first high-speed flip-flop and the second high-speed flip-flop comprise a high-speed flip-flop circuit respectively, and the high-speed flip-flop circuit comprises:
a first PMOS transistor, a first NMOS transistor, an inverter and a logic gate, the source of the first PMOS transistor is connected to a power supply terminal, the gate is connected to the output of the first logic gate, the drain is connected to a first node, and the drain of the NMOS transistor is connected to the first node and the gate is connected to the output terminal of the logic gate, the source is connected to the common connection end, one terminal of the inverter is connected to the first node, and the other terminal is used as the output terminal of the high-speed flip-flop circuit.

2 more elements

A successive approximation analog-to-digital converter (SAR ADC) comprising:

a comparator;
a capacitive digital-to-analog converter (CDAC);
and
a logic control circuit, the logic control circuit comprises:
a shift register;
and
a data register consisting of data register units, the data register unit comprising:
a first high-speed flip-flop;
a second high-speed flip-flop;
a first logic gate,
wherein, the first high-speed flip-flop and the second high-speed flip-flop comprise a high-speed flip-flop circuit respectively, and the high-speed flip-flop circuit comprises:
a first PMOS transistor, a first NMOS transistor, an inverter and a logic gate, the source of the first PMOS transistor is connected to a power supply terminal, the gate is connected to the output of the first logic gate, the drain is connected to a first node, and the drain of the NMOS transistor is connected to the first node and the gate is connected to the output terminal of the logic gate, the source is connected to the common connection end, one terminal of the inverter is connected to the first node, and the other terminal is used as the output terminal of the high-speed flip-flop circuit.

9 more elements

An electronic device comprising a SAR ADC, the SAR ADC comprising a data register for Merged Capacitor switching (MCS), the data register comprising a high-speed flip-flop circuit that generates a capacitor connection signal based on a bit comparison result, wherein the high-speed flip-flop circuit comprises:

a first PMOS transistor, a first NMOS transistor, an inverter, and a logic gate, wherein the source of the first PMOS transistor is connected to a power supply terminal, the gate is connected to the bit comparison result, and the drain is connected to a first node, the drain of the first NMOS transistor is connected to the first node, the gate is connected to the output terminal of the logic gate, the source is grounded (VSS), one terminal of the inverter is connected to the first node, and the other terminal is used as the output of the high-speed flip-flop circuit.

Dependencies are inferred from the claim text.

Data register unit, SAR ADC and electronic device

Life of this patent

Data register unit, SAR ADC and electronic device

Life of this patent

Abstract

Claims20