Fault detection within an analog-to-digital converter

A circuit comprising:

• an analog-to-digital converter (ADC) having selectable first and second analog channel inputs;
• a window comparator configured to compare a digital value output by the ADC to first and second threshold values defining a window and to assert a trigger signal in response to the digital value being outside the window;
• a programmable clock circuit configured to provide a clock signal to the ADC;
• a controller configured to generate, in response to assertion of the trigger signal, a sample rate control signal to cause the programmable clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs;
• and
• comparison circuitry configured to compare a first digital output from the ADC to a second digital output from the ADC.

A method, comprising:

• applying a clock signal having a first frequency to an analog-to-digital converter (ADC);
• increasing the frequency of the clock signal to a second frequency in response to a first control signal;
• and
• comparing a first digital value output by the ADC to a second digital value output by the ADC, the first and second digital values output by the ADC in succession and representing a pair;
• and
• asserting a fault signal responsive to a difference between the pair of digital values being greater than a threshold.