Systems and method of compensating for nonlinear capacitance in converters
AssigneeAvago Technologies International Sales Pte. Limited
InventorsJan Mulder, Frank Van der Goes, Mohammadreza Mehrpoo, Sijia Wang
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Abstract
Described herein are systems and methods related to a converter includes a number of unit cells. The unit cells each include a first transistor and a second transistor. The first transistor is coupled in series with an output of the unit cell, and the second transistor is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor. The converter can be a voltage or current mode digital to analog converter.
Claims19
A converter, comprising:
- a plurality of unit cells, wherein the unit cells each comprise a first transistor and a second transistor, wherein the first transistor is coupled in series with an output of a unit cell and wherein the second transistor is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor wherein a gate of the second transistor is coupled to the output and a bias circuit is coupled between a drain of the second transistor and a source of the second transistor.
A converter, comprising:
- a plurality of unit cells, wherein the unit cells each comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitive element and a second capacitive element, the first transistor being configured to drive a signal at a first output, the second transistor being configured to drive a signal at a second output, wherein the third transistor is configured to reduce an output swing experienced by the first transistor, wherein the fourth transistor is configured to reduce an output swing experienced by the second transistor, wherein the first capacitive element is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor, wherein the second capacitive element is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the second transistor.
A method of reducing a nonlinear capacitive response of converter, comprising:
- a plurality of unit cells, wherein the unit cells each comprise a first transistor and a second transistor, wherein the first transistor is coupled in series with a first output of a unit cell, wherein the second transistor is coupled in series with a second output of the unit cell, the method comprising:
- biasing a first active element so that the first active element has a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor;
- and
- biasing a second active element so that the second active element has a capacitive characteristic that reduces a non-linear capacitive characteristic of the second transistor.
Dependencies are inferred from the claim text.