Phase-locked loop circuit with frequency holding and reference frequency smooth switching

A phase-locked loop circuit with frequency holding and reference frequency smooth switching, comprising:

• a clock signal processing module, and a phase-locked loop function module and a Vcrtl voltage control module which are respectively connected with the clock signal processing module, wherein the phase-locked loop function module is connected with the Vcrtl voltage control module;
• the clock signal processing module is configured for receiving and monitoring an external reference clock signal CLKref in real time, and simultaneously generating a feedback clock signal CLKfb;
• and according to a phase difference between the external reference clock signal CLKref and the feedback clock signal CLKfb, the phase-locked loop function module and the Vcrtl voltage control module connected with the clock signal processing module are controlled by outputting a pulse signal, and a controlled reference clock signal is provided for a subsequent circuit connected with the phase-locked loop circuit;
• the clock signal processing module comprises a clock signal loss detection module (10), a digital-to-time converter (11) and a time-to-digital converter (12);
• an input end (101) of the clock signal loss detection module (10) and an input end (111) of the digital-to-time converter (11) are respectively used as an input end of the clock signal processing module for receiving the reference clock signal CLKref;
• an output end (102) of the clock signal loss detection module (10) is connected with a control end (123) of the time-to-digital converter (12);
• and the output end (102) of the clock signal loss detection module (10) is used as a first output end of the time signal processing module to be connected with the Vcrtl voltage control module and the phase-locked loop function module respectively;
• an output end (124) of the time-to-digital converter (12) is connected with a control end (112) of the digital-to-time converter (11) for controlling an output delay of the digital-to-time converter (11);
• an output end (113) of the digital-to-time converter (11) is used as a second output end of the time signal processing module to be connected with the phase-locked loop function module for outputting a new clock signal CLKNEW with a same frequency as the reference clock signal CLKref and a phase difference controlled by the output delay of the digital-to-time converter (11);
• and the output end (113) of the digital-to-time converter (11) is connected with a second input end (122) of the time-to-digital converter (12);
• a first input end (121) of the time-to-digital converter (12) is used as a feedback signal receiving end of the clock signal processing module, and receives the feedback clock signal CLKfb output by the phase-locked loop function module;
• the phase-locked loop function module comprises a phase discriminator (13), a charge pump (14), a loop filter (15), a voltage-controlled oscillator (16) and a connection frequency divider (17);
• a first output end (133) of the phase discriminator (13) is connected with a first input end (141) of the charge pump (14) for the phase discriminator (13) to output the new clock signal CLKNEW to the charge pump (14), a second output end (134) of the phase discriminator is connected with a second input end (142) of the charge pump (14) for the phase discriminator (13) to output the feedback clock signal CLKfb to the charge pump (14), and a control signal of the charge pump is generated according to a phase difference between the CLKNEW and the CLKfb at the same time;
• an output end (143) of the charge pump (14) is used as a first output end of the phase-locked loop function module to be connected with the voltage control module;
• the phase discriminator (13) is used as a first input end of the phase-locked loop function module, and receives an output signal of the output end (113) of the digital-to-time converter (11);
• a control end (144) of the charge pump (14) receives an output signal of the output end (102) of the clock signal loss detection module (10);
• an input end (151) of the loop filter (15) receives an output signal of the charge pump (14) through the voltage control module;
• and an output end (152) of the loop filter (15) is connected with an input end (161) of the voltage-controlled oscillator (16);
• an output end (162) of the voltage-controlled oscillator (16) is connected with an input end (171) of the connection frequency divider (17), and an output end (172) of the connection frequency divider (17) is used as a second output end of the phase-locked loop function module to be connected with the first input end (121) of the time-to-digital converter (12);
• and an output end (162) of the voltage-controlled oscillator (16) is used as an output end of the phase-locked loop function module to provide a controlled reference clock signal for a subsequent circuit connected with a phase-locked loop circuit;
• the Vcrtl voltage control module comprises a comparator (18), a reference voltage generation module (19) and a switch (20);
• an output end (191) of the reference voltage generation module (19) is connected with a first input end (181) of the comparator (18) for outputting a reference voltage Vref to the comparator (18);
• the output end (191) of the reference voltage generation module (19) is connected with a first input end (201) of the switch (20);
• a second input end (182) of the comparator (18) is connected with a third input end (203) of the switch (20);
• the switch (20) is used as an input end of the Vcrtl voltage control module, and receives an output signal of the output end (102) of the clock signal loss detection module (10);
• and a third input end (203) of the switch (20) is connected with the input end (151) of the loop filter (15);
• and
• an output end (183) of the comparator (18) is used as an output end of the Vcrtl voltage control module to be connected with a capacitor array control end (163) of the voltage-controlled oscillator (16).