Frequency-detecting circuit, duty-cycle corrector, and electronic device

A Duty-Cycle Corrector (DCC), characterized by comprising:

• a filtering circuit, an input terminal of the filtering circuit being configured to input a first clock signal;
• a DC bias amplifying circuit, an input terminal of the DC bias amplifying circuit being coupled to an output terminal of the filtering circuit, and an output terminal of the DC bias amplifying circuit being configured to output a second clock signal;
• and
• an attenuation adjusting circuit, an input terminal of the attenuation adjusting circuit being coupled to the input terminal of the filtering circuit, and an output terminal of the attenuation adjusting circuit being coupled to the input terminal of the DC bias amplifying circuit;
• wherein the attenuation adjusting circuit comprises a frequency-detecting circuit comprising:
• a control-signal generating circuit, configured to receive a to-be-detected clock signal and generate a first control signal corresponding to the to-be-detected clock signal and a second control signal delayed relative to the first control signal;
• a charging and discharging path, coupled to the control-signal generating circuit, and performing a charging process or a discharging process under control of the second control signal, wherein during a period with a pulse width when the second control signal is at a high level, the charging and discharging path performs the discharging process, and the charging and discharging path performs the charging process during another period when the second control signal is at a low level;
• and
• a control-voltage generating circuit, coupled to an output terminal of the charging and discharging path and the control-signal generating circuit, and configured to sample values of a voltage of an output terminal of the charging and discharging path before the discharging process during a period with a pulse width when the first control signal is at the high level, to output a corresponding first voltage signal;
• wherein the first clock signal is as the to-be-detected clock signal, the attenuation adjusting circuit performs an attenuation adjusting process for a signal output by the filtering circuit based on a frequency of the first clock signal.

An electronic device, comprising a frequency-detecting circuit, wherein the frequency-detecting circuit comprises:

• a control-signal generating circuit, configured to receive a to-be-detected clock signal and generate a first control signal corresponding to the to-be-detected clock signal and a second control signal delayed relative to the first control signal;
• a charging and discharging path, coupled to the control-signal generating circuit, and performing a charging process or a discharging process under control of the second control signal, wherein during a period with a pulse width when the second control signal is at a high level, the charging and discharging path performs the discharging process, and the charging and discharging path performs the charging process during another period when the second control signal is at a low level;
• and
• a control-voltage generating circuit, coupled to an output terminal of the charging and discharging path and the control-signal generating circuit, and configured to sample values of a voltage of an output terminal of the charging and discharging path before the discharging process during a period with a pulse width when the first control signal is at the high level, to output a corresponding first voltage signal.