Clock duty cycle measurement
AssigneeCadence Design Systems, Inc.
InventorsPrakash Kumar Lenka, Hari Anand Ravi, Jitendra Kumar Yadav
Life of this patent
Estimating the term…
Loading patent…
AssigneeCadence Design Systems, Inc.
InventorsPrakash Kumar Lenka, Hari Anand Ravi, Jitendra Kumar Yadav
Estimating the term…
The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.
A circuit for duty cycle measurement, the circuit comprising:
A method for duty cycle measurement, the method comprising:
A system for duty cycle measurement and correction, the system comprising:
Dependencies are inferred from the claim text.