Latch circuit and memory device

A memory device, comprising:

• a memory cell;
• and
• a control circuit coupled to control an operation of the memory cell, the control circuit comprising:
• a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal;
• and
• an input latch coupled to the latch clock generator to receive the latched clock signal, the input latch configured to generate a latched output signal based on the latched clock signal and an input signal,
• wherein
• the enable signal corresponds to a write enable signal to enable or disable writing to the memory cell,
• in response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal, and
• in response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.

A latch circuit, comprising:

• a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal;
• an input latch coupled to the latch clock generator to receive the latched clock signal, the input latch configured to generate a latched output signal based on the latched clock signal and an input signal;
• and
• an enable latch configured to generate the first enable signal based on the clock signal and a second enable signal,
• wherein the latch clock generator is coupled to the enable latch to receive the first enable signal,
• wherein, in response to the first enable signal having a first disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal, and
• wherein the enable latch is configured to hold the first disabling logic level of the first enable signal in a first duration longer than a second duration of a corresponding second disabling logic level of the second enable signal.