Frequency divider, electronic device and frequency dividing method

An electronic device, comprising a frequency divider, wherein the frequency divider comprises a duty cycle correction circuit and a frequency dividing circuit, wherein

• the duty cycle correction circuit is configured to receive a first clock signal, and perform a first processing on the first clock signal to generate a first processed signal, wherein a period of the first clock signal is a first period, a period of the first processed signal is a second period, and the second period is one P-th of the first period, wherein P is an integer greater than 1,
• the frequency dividing circuit is configured to receive the first processed signal, and perform a second processing on the first processed signal to generate a second processed signal, wherein a period of the second processed signal is a third period, and the third period is Q times the second period, wherein Q is an integer greater than 1, and
• the duty cycle correction circuit is further configured to receive the second processed signal, and perform a third processing on the second processed signal to generate a third processed signal, wherein a period of the third processed signal is a fourth period, and the fourth period is P times the third period,
• wherein the duty cycle correction circuit comprises a frequency multiplying sub-circuit, and the frequency multiplying sub-circuit is configured to perform the first processing on the first clock signal to obtain the first processed signal,
• wherein the frequency multiplying sub-circuit comprises an XOR sub-circuit and a delay sub-circuit,
• the delay sub-circuit receives the first clock signal, and performs a delay processing on the first clock signal to obtain a first delay signal, and
• the XOR sub-circuit receives the first clock signal and the first delay signal, and performs an XOR operation on the first clock signal and the first delay signal to obtain the first processed signal.

A frequency dividing method, comprising:

• performing a first processing on a first clock signal to generate a first processed signal, wherein a period of the first clock signal is a first period, a period of the first processed signal is a second period, and the second period is one P-th of the first period, wherein P is an integer greater than 1;
• performing a second processing on the first processed signal to generate a second processed signal, wherein a period of the second processed signal is a third period, and the third period is Q times the second period, wherein Q is an integer greater than 1;
• and
• performing a third processing on the second processed signal to generate a third processed signal, wherein a period of the third processed signal is a fourth period, and the fourth period is P times the third period,
• wherein performing the first processing on the first clock signal to generate the first processed signal comprises:
• performing a delay processing on the first clock signal to obtain a first delay signal;
• and
• performing an XOR operation on the first clock signal and the first delay signal to obtain the first processed signal.