Semiconductor device for logic and memory co-optimization

A circuit, comprising:

• a logic unit cell including a first fin in a P-type region and second fin in an N-type region, wherein a gate is disposed over the first fin and the second fin, wherein a first source contact and a second source contact are disposed adjacent to, and on a same side of, the gate and provide contact to respective ones of the first fin and the second fin, wherein a first X-pitch ‘X1’ of the logic unit cell is parallel to a first routing direction of the gate, and wherein the first X-pitch ‘X1’ is defined from a left edge of the first source contact to a right edge of the second source contact;
• and
• a memory unit cell including a plurality of fins and a plurality of gates, wherein a second X-pitch ‘X2’ of the memory unit cell is parallel to a second routing direction of the plurality of gates;
• wherein the second X-pitch ‘X2’ is equal to the first X-pitch ‘X1’.

A semiconductor device, comprising:

• a CMOS logic device including a first transistor with a first fin width, the CMOS logic device having a first isolation spacing between a first N+ region and a first N-well (NW) region and between a first P+ region and a first P-well (PW) region;
• and
• a static random-access memory (SRAM) device including a second transistor with a second fin width, the SRAM device having a second isolation spacing between a second N+ region and a second NW region and between a second P+ region and a second PW region;
• wherein the first fin width is less than the second fin width, and wherein the first isolation spacing is greater than the second isolation spacing.