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US 12,184,279 B2Granted
Methods and apparatus to perform CML-to-CMOS deserialization
AssigneeTexas Instruments Incorporated
InventorsNithin Sathisan Poduval, Abishek Manian, Roland Nii Ofei Ribeiro
Life of this patent
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Abstract
An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.
Claims20
A system comprising:
- a first deserializer including an input, a first output and a second output, the input configured to receive a current-mode logic (CML) data stream;
- a first deserializer array coupled to the first deserializer, the first deserializer array including:
- a second deserializer including a first input and a third output, the first input coupled to the first output;
- and
- a third deserializer including a second input and a fourth output, the second input coupled to the third output;
- and
- a second deserializer array coupled to the first deserializer array, the second deserializer array including:
- a fourth deserializer including a third input and a fifth output and a sixth output, the third input coupled to the second output;
- and
- a fifth deserializer including a fourth input and a seventh output and an eight output, the fourth input coupled to the third output, and a complementary metal-oxide-semiconductor (CMOS) data stream is configured to be generated at each of the fifth, sixth, seventh and eight output.
7 more elements
A method comprising:
- configuring a first deserializer to generate a plurality of secondary current-mode logic (CML) data streams in response to a primary current-mode logic (CML) data stream;
- and
- configuring a second deserializer to generate two complementary metal-oxide-semiconductor (CMOS) data streams in response to a secondary CML data stream of the plurality of secondary CML data streams.
Dependencies are inferred from the claim text.