Synthesis driven for minimum leakage with new standard cells

A complementary metal-oxide-semiconductor (CMOS) logic gate, comprising:

• a first p-channel transistor coupled between a voltage source terminal of the CMOS logic gate and an output terminal of the CMOS logic gate, the first p-channel transistor configured to be body biased;
• a first n-channel transistor coupled between the output terminal and reference ground;
• a series p-channel transistor coupled between the output terminal and the first p-channel transistor, wherein the series p-channel transistor is configured to be body biased;
• and
• a shunt n-channel transistor coupled between the output terminal and reference ground, wherein a gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.

A device, comprising an integrated circuit, the integrated circuit having:

• a complementary metal-oxide-semiconductor (CMOS) logic gate including a first p-channel transistor and a first n-channel transistor, wherein the first p-channel transistor is configurable to be body biased;
• a series p-channel transistor coupled between an output terminal of the CMOS logic gate and the first p-channel transistor, wherein the series p-channel transistor is configurable to be body biased;
• and
• a shunt n-channel transistor coupled between the output terminal of the CMOS logic gate and reference ground, wherein a gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low power operating mode of the CMOS logic gate.