Gate drive circuit and drive method for power semiconductor device

A gate drive circuit for a power semiconductor device, comprising:

• a power semiconductor device, wherein the power semiconductor device is a transistor that is provided with a first gate and a second gate, the first gate and the second gate are not connected to each other, the second gate and a source of the transistor are not connected to each other, the first gate is disposed above a channel region of the transistor and is configured to control the channel region, and the second gate is disposed above a field oxide of the transistor and is configured to control a drift region of the transistor;
• a first gate driver, wherein a control terminal of the first gate driver is configured to connect a control signal, a voltage input terminal of the first gate driver is connected to a first voltage, a voltage output terminal of the first gate driver is electrically connected to the first gate, and the first voltage is an operating voltage of the first gate;
• and
• a second gate driver, wherein a control terminal of the second gate driver is configured to connect the control signal, a voltage input terminal of the second gate driver is connected to a second voltage, a voltage output terminal of the second gate driver is electrically connected to the second gate, and the second voltage is an operating voltage of the second gate;
• when the first gate driver receives the control signal which is at a first level, the first gate is connected to the first voltage to make the first gate control the channel region, so that in a first duration, the transistor first enters a Miller plateau, and then enters an ohmic region from the Miller plateau;
• and
• when the second gate driver receives the control signal which is at the first level, the second gate is connected to the second voltage after the first duration, so that the second gate controls the drift region of the transistor to form an accumulation layer.