Self-aligned contacts for thin film transistors

A computing device comprising:

• a processor;
• a memory device coupled to the processor, wherein the processor or the memory device includes a transistor, and the transistor includes:
• a U-shaped channel above a substrate, wherein the U-shaped channel includes a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area, the first channel wall intersects with the channel bottom at a first end and intersects with the source area at a second end, and the second channel wall intersects with the channel bottom at a first end and intersects with the drain area at a second end;
• a gate dielectric layer in contact with the channel bottom;
• a gate electrode in contact with the gate dielectric layer, wherein the gate electrode extends laterally beyond a lowermost portion of an outermost side of the first channel wall and laterally beyond a lowermost portion of an outermost side of the second channel wall of the U-shaped channel;
• and
• a source electrode in direct physical contact with a top surface of the source area but not in direct physical contact with a bottom surface of the source area, and a drain electrode in direct physical contact with a top surface of the drain area but not in direct physical contact with a bottom surface of the drain area, wherein a bottommost surface of the source electrode is above an uppermost surface of the source area, and a bottommost surface of the drain electrode is above an uppermost surface of the drain area, and wherein the source electrode is entirely within a width of the source area along a direction from the source area to the drain area and is vertically overlapping with the first channel wall of the U-shaped channel structure, and the drain electrode is entirely within a width of the drain area along the direction from the source area to the drain area and is vertically overlapping with the second channel wall of the U-shaped channel structure.