Vertical field effect transistor with low-resistance bottom source-drain contact

A semiconductor structure comprising:

• a fin extending upward from a substrate;
• a first portion of an epitaxially grown bottom source/drain region being parallel to and in direct contact with a portion of the substrate adjacent to the fin;
• a second portion of the epitaxially grown bottom source/drain region being perpendicular to the substrate and in direct contact with a bottom portion of the fin;
• a metal silicide layer extending horizontally above the first portion of the epitaxially grown source/drain region parallel to the substrate, the metal silicide layer being partially abutted by the second portion of the epitaxially grown bottom source/drain region, the metal silicide layer comprising a bottom surface and opposing sidewalls, the bottom surface of the metal silicide layer being above and in direct contact with the first portion of the epitaxially grown source/drain region, the opposing sidewalls of the metal silicide layer being in direct contact with the second portion of the epitaxially grown bottom source/drain region for preventing the metal silicide layer to contact the fin, a top surface of the metal silicide layer extending in a plane for an entire distance between the opposing sidewalls of the metal silicide layer and being coplanar with a top surface of the second portion of the epitaxially grown bottom source/drain region;
• a bottom spacer above and in direct contact with the coplanar top surface of the metal silicide layer and the top surface of the second portion of the epitaxially grown bottom source/drain region;
• a gate dielectric layer in direct contact with sidewalls of the fin;
• a gate metal layer in direct contact with the gate dielectric layer;
• and
• a top spacer above and in direct contact with the gate metal layer and the bottom spacer.