Fin field-effect transistor with a gate structure having a dielectric protection layer

A semiconductor device, comprising:

• a semiconductor fin;
• a lightly doped drain region in the semiconductor fin;
• a metal gate over the semiconductor fin;
• a gate spacer over the semiconductor fin and extending along a sidewall of the metal gate, wherein the gate spacer includes a lower portion and an upper portion over the lower portion, and wherein the sidewall of the metal gate is adjacent the lower portion;
• a source/drain feature in the lightly doped drain region, wherein the gate spacer is vertically aligned with a sidewall of the lightly doped drain region;
• a dielectric protection layer having a sidewall adjacent to the upper portion of the gate spacer and a bottom surface contacting a top surface of the metal gate, the dielectric protection layer including a metal silicate material;
• and
• a dielectric layer fully embedded in the dielectric protection layer, such that top surfaces of the dielectric protection layer and the dielectric layer are coplanar, the dielectric layer including a low-k dielectric material.

A semiconductor device, comprising:

• a semiconductor fin;
• a gate spacer over the semiconductor fin, wherein the gate spacer includes an upper portion over a lower portion;
• a gate dielectric over the semiconductor fin;
• a metal gate over the gate dielectric and adjacent the lower portion of the gate spacer, wherein a top surface of the gate spacer is above a top surface of each of the metal gate and the gate dielectric;
• a source/drain feature in the semiconductor fin adjacent to the metal gate;
• an etch-stop layer over the source/drain feature, a portion of the etch-stop layer directly contacting both a sidewall of the gate spacer and a sidewall of the source/drain feature;
• a dielectric protection layer over the metal gate, wherein the dielectric protection layer includes a sidewall portion extending along the upper portion of the gate spacer and a bottom portion extending across the top surface of each of the metal gate and the gate dielectric, and wherein the dielectric protection layer includes a metal silicate;
• an interlayer dielectric (ILD) layer adjacent the gate spacer, wherein top surfaces of the ILD layer and the dielectric protection layer are leveled;
• and
• a source/drain contact embedded in the ILD layer, a portion of the ILD layer laterally separating the source/drain contact from the gate spacer.