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US 12,183,822 B2Granted
MOSFET structure with controllable channel length by forming lightly doped drains without using ion implantation
AssigneesInvention And Collaboration Laboratory Pte. Ltd., Etron Technology, Inc.
InventorChao-Chun Lu
Life of this patent
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Abstract
The present invention provides a new MOSFET structure with controllable channel length by forming lightly doped drains without using ion implantation. The MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a gate structure over the semiconductor surface, a channel region under the semiconductor surface, and a first conductive region electrically coupled to the channel region. The first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate.
Claims13
A MOSFET structure comprising:
- a semiconductor wafer substrate with a semiconductor surface;
- a gate structure over the semiconductor surface;
- a channel region under the semiconductor surface;
- a first conductive region surrounded by a shallow trench isolation (STI) region and electrically coupled to the channel region;
- and
- a first trench formed below the semiconductor surface and defined by an edge of the channel region and an edge of the STI region which face with each other, wherein the first trench includes a first edge facing the edge of the channel region and a second edge opposing to the first edge, the second edge is aligned with the edge of the STI region;
- wherein the first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate and a heavily doped drain region;
- the lightly doped drain region at least laterally extends from the first edge of the first trench and the heavily doped drain region at least laterally extends from the lightly doped drain region, and the first trench accommodates the lightly doped drain region;
- wherein the first conductive region comprises a first most external edge facing to the edge of the channel region and a second most external edge opposite to the first most external edge, wherein the second most external edge is faced to and limited by the edge of the STI region, wherein the first edge of the first trench is controllable to align or substantially align with an edge of the gate structure.
6 more elements
A MOSFET structure comprising:
- a semiconductor wafer substrate with a semiconductor surface;
- a gate structure over the semiconductor surface;
- a channel region under the semiconductor surface;
- a first conductive region surrounded by a STI region, comprising a lightly doped drain region independent from the semiconductor wafer substrate and a heavily doped drain region, and electrically coupled to the channel region;
- a first trench formed below the semiconductor surface and defined by an edge of the channel region and an edge of the STI region which face with each other, wherein the first trench includes a first edge facing the edge of the channel region and a second edge opposing to the first edge, the second edge is aligned with the edge of the STI region, wherein the lightly doped drain region at least laterally extends from the first edge of the first trench;
- and the heavily doped drain region at least laterally extends from the lightly doped drain region;
- and
- wherein the first edge of the first trench is controlled by a thickness of a thermal oxidation layer;
- wherein the first conductive region comprises a first most external edge facing to the edge of the channel region and a second most external edge opposite to the first most external edge, wherein the second most external edge is faced to and limited by the edge of the STI region.
6 more elements
A MOSFET structure comprising:
- a semiconductor wafer substrate with a semiconductor surface;
- a gate structure over the semiconductor surface;
- a channel region under the semiconductor surface;
- a first conductive region surrounded by a STI region and electrically coupled to the channel region;
- and
- a first trench formed below the semiconductor surface and defined by an edge of the channel region and an edge of the STI region which face with each other, wherein the first trench includes a first edge facing the edge of the channel region and a second edge opposing to the first edge, the second edge is aligned with the edge of the STI region;
- wherein the first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate and a heavily doped drain region;
- and the first trench accommodates the lightly doped drain region;
- wherein a vertical edge of the lightly doped drain region is parallel to a vertical edge of the gate structure;
- wherein the first conductive region comprises a first most external edge facing to the edge of the channel region and a second most external edge opposite to the first most external edge, wherein the second most external edge is faced to and limited by the edge of the STI region;
- the first most external edge is controllable to align or substantially align with an edge of the gate structure.
8 more elements
Dependencies are inferred from the claim text.