Type III-V semiconductor device with multi-layer barrier region

A semiconductor device, comprising:

• a semiconductor substrate comprising a barrier region of AlGaN semiconductor material and a channel region of GaN or AlGaN disposed below the barrier region, the barrier region forming a heterojunction with the channel region such that a two-dimensional charge carrier gas is disposed in the channel region near the heterojunction;
• source and drain electrodes that are each in ohmic contact with the two-dimensional charge carrier gas;
• and
• a gate structure that is configured to control a conductive connection between the source and drain electrodes,
• wherein the barrier region comprises a first barrier layer and a second barrier layer,
• wherein in a central portion of the semiconductor device that overlaps with the gate structure the second barrier layer is the only one of the first and second barrier layers that is disposed over the channel region,
• wherein in outer lateral portions of the semiconductor device that are disposed on either side of the central portion the first barrier layer is disposed over the channel region,
• wherein the first and second barrier layers are each layers of AlGaN, and
• wherein the aluminum content of the semiconductor device in the central portion of the semiconductor device between the gate structure and the channel region is higher than the aluminum content of the first barrier layer.

A method of forming a semiconductor device, the method comprising:

• providing a semiconductor substrate comprising a barrier region of III-V semiconductor material and a channel region of III-V semiconductor material disposed below the barrier region, the barrier region forming a heterojunction with the channel region such that a two-dimensional charge carrier gas is disposed in the channel region near the heterojunction;
• forming a source and drain electrodes that are each in ohmic contact with the two-dimensional charge carrier gas;
• and
• forming a gate structure that is configured to control a conductive connection between the source and drain electrodes,
• wherein the barrier region comprises a first barrier layer and a second barrier layer,
• wherein in a central portion of the semiconductor device that overlaps with the gate structure the second barrier layer is the only one of the first and second barrier layers that is disposed over the channel region,
• wherein in outer lateral portions of the semiconductor device that are disposed on either side of the central portion the first barrier layer is disposed over the channel region,
• wherein the first and second barrier layers are each III-V semiconductor alloys comprising a first type III element and a second type III element, and
• wherein a molar fraction of the second type III element in the central portion of the semiconductor device between the gate structure and the channel region is higher than in the first barrier layer.