A cell structure of a semiconductor device, the cell structure comprising:
- a semiconductor substrate of a first conductivity type;
- a plurality of first trench units arranged in the top surface region of the semiconductor substrate, the plurality of first trench units spaced apart, a conductive material filled in the plurality of first trench units and isolated from the semiconductor substrate by a first dielectric material;
- a carrier barrier region of the first conductivity type arranged to abut the bottoms of the plurality of first trench units or close to side edges of the bottoms of the plurality of first trench units and isolated from the conductive material by the first dielectric material, wherein the doping concentration of the carrier barrier region is higher than the doping concentration of the semiconductor substrate;
- a first source-body region of a second conductivity type arranged in gaps among the plurality of first trench units, wherein more than one source regions of the first conductivity type are arranged in the first source-body region, wherein the first source-body region and the source regions are located in the top surface region of the semiconductor substrate;
- a first metal layer arranged at the top of the semiconductor substrate, wherein the first metal layer is in contact with the first source-body region and the source regions;
- a second dielectric material arranged at the top of the semiconductor substrate, adjacent to or abutting the first metal layer, wherein the second dielectric material covers some or all of the trench openings of the plurality of first trench units;
- a first semiconductor region arranged in the bottom region of the semiconductor substrate;
- a second metal layer arranged in contact with the first semiconductor region;
- a first electric field shielding region of the a-second conductivity type arranged in the semiconductor substrate in a depth equal or close to the depth of the carrier barrier region;
- a plurality of second trench units arranged in the top surface region of the semiconductor substrate and at the outer side of the plurality of first trench units, wherein the conductive material is filled in the plurality of second trench units and is isolated from the semiconductor substrate by a third dielectric material;
- a second source-body region arranged in the gaps among the plurality of second trench units and located on the surface of the semiconductor substrate;
- a third metal layer arranged at the top of the semiconductor substrate, wherein the third metal layer is in contact with the second source-body region and a part of the surface or the entire surface of the second source-body region contacts the third metal layer;
- and
- a fourth dielectric material arranged at the top of the semiconductor substrate, abutting the third metal layer, the fourth dielectric material covering some or all of the trench openings of the plurality of second trench units;
- wherein the first electric field shielding region is arranged to abut the bottoms of the plurality of second trench units or adjacent to the side edges of the bottoms of the plurality of second trench units, and is isolated from the conductive material by the third dielectric material.