Dual-gated memtransistor crossbar array, fabricating methods and applications of same

A crossbar array comprised of M columns and N rows of memtransistors, each of M and N being an integer greater than zero, comprising:

• a bottom gate electrode layer;
• a bottom dielectric layer formed on the bottom gate electrode layer;
• a polycrystalline monolayer film formed of an atomically thin material formed on the bottom dielectric layer, wherein the atomically thin material comprises two-dimensional (2D) semiconductor material, wherein the polycrystalline monolayer film contains grains having an average grain size of about 1 μm2;
• M+1 source-drain electrodes spatial-apart formed on the polycrystalline monolayer film along a column direction, wherein the polycrystalline monolayer film is patterned according to the M+1 source-drain electrodes to define M columns and N rows of channels therein, such that each two neighboring source-drain electrodes are coupled with N channels of a respective channel column between said two neighboring source-drain electrodes;
• a top dielectric layer formed on the polycrystalline monolayer film and extended over the M+1 source-drain electrodes, such that each of the M+1 source-drain electrodes is disposed between the bottom dielectric layer and the top dielectric layer;
• and
• N top gate electrodes formed on the top dielectric layer, crossing over the M+1 source-drain electrodes along a row direction, such that each top gate electrode is capacitively coupled with M channels of a respective channel row,
• wherein each memtransistor is a dual gated memtransistor characterized with a switching ratio between a low resistance state (LRS) and a high resistance state (HRS), wherein the switching ratio is a ratio of current (ILRS) of the dual gated memtransistor at the LRS to that (IHRS) of the dual gated memtransistor at the HRS, and wherein each dual gated memtransistor is configured such that the switching ratio increases with increasing a voltage of the bottom gate electrode.