Semiconductor device with gate isolation features and fabrication method of the same

A semiconductor device, comprising:

• a plurality of channel members over a backside dielectric feature;
• a gate structure wrapping around each of the channel members;
• a first isolation feature disposed on a first sidewall of the gate structure, the first isolation feature extending vertically from a bottom surface of the backside dielectric feature to a top surface of the gate structure;
• and
• a second isolation feature disposed on a second sidewall of the gate structure, the second isolation feature extending vertically from the bottom surface of the backside dielectric feature to the top surface of the gate structure.

A semiconductor device, comprising:

• a first plurality of channel members over a first backside dielectric feature;
• a second plurality of channel members over a second backside dielectric feature;
• a first source/drain feature abutting the first plurality of channel members and over the first backside dielectric feature;
• a second source/drain feature abutting the second plurality of channel members and over the second backside dielectric feature;
• a first gate structure wrapping around each of the first plurality of channel members;
• a second gate structure wrapping around each of the second plurality of channel members;
• a metal capping layer disposed on the first and second gate structures;
• a first isolation feature includes a first portion stacked between the first and second gate structures and a second portion stacked between the first and second source/drain features;
• and
• a second isolation feature through the metal capping layer and landing on the first isolation feature.