Threshold voltage modulation for gate-all-around FET architecture
AssigneeApplied Materials, Inc.
InventorsSteven C. H. Hung, Benjamin Colombeau, Myungsun Kim, Srinivas Gandikota, Yixiong Yang, Jacqueline Samantha Wrench, Yong Yang
Life of this patent
Estimating the term…
Abstract
A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.
Claims20
A method of forming a gate stack structure, the method comprising:
- forming a dipole metal layer on a high-gate dielectric layer on a semiconductor structure formed on a substrate;
- annealing the dipole metal layer;
- and
- removing the dipole metal layer, wherein
- the dipole metal layer comprises dopants in the high-K gate dielectric layer.
A method of forming a gate stack structure, the method comprising:
- forming a p-type work function adjusting layer on a high-k gate dielectric layer on a semiconductor structure formed on a substrate;
- forming an n-type work function adjusting layer on the high-K gate dielectric layer;
- and
- forming a metal gate electrode on the p-type work function adjusting layer and the n-type work function adjusting layer, wherein
- the p-type work function adjusting layer comprises p-doped conductive material, and
- the n-type work function adjusting layer comprises n-doped conductive material.
A method of forming a gate stack structure on a semiconductor structure, the method comprising:
- forming an interfacial layer on a semiconductor structure;
- forming a high-K gate dielectric layer on the interfacial layer;
- forming a dipole metal layer comprising dopants in the high-gate dielectric layer on the high-K gate dielectric layer;
- annealing the dipole metal layer;
- removing the dipole metal layer;
- forming a first high-K dielectric cap layer on the high-K gate dielectric layer;
- forming a p-type work function adjusting layer on the high-K gate dielectric layer;
- forming an n-type work function adjusting layer on the high-K gate dielectric layer;
- forming a second high-K dielectric cap layer on the p-type work function adjusting layer and the n-type work function adjusting layer;
- and
- forming a metal gate electrode on the second high-K dielectric cap layer, wherein
- the p-type work function adjusting layer comprises p-doped conductive material, and
- the n-type work function adjusting layer comprises n-doped conductive material.
Dependencies are inferred from the claim text.