Profile control of channel structures for semiconductor devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChao-Wei Hsu
Life of this patent
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Abstract
The present disclosure describes a semiconductor device having a channel structure with profile control. The semiconductor device includes a fin structure on a substrate. The fin structure includes a bottom portion on the substrate and a top portion including multiple semiconductor layers. The semiconductor device further includes a gate structure wrapped around the multiple semiconductor layers and a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the plurality of semiconductor layers. The S/D structure extends into end portions of the multiple semiconductor layers.
Claims20
A semiconductor device, comprising:
- a fin structure on a substrate, wherein the fin structure comprises a bottom portion on the substrate and a top portion comprising a plurality of semiconductor layers, and wherein end portions of the plurality of semiconductor layers have a recessed surface;
- a gate structure wrapped around the plurality of semiconductor layers;
- and
- a source/drain (S/D) structure on the bottom portion of the fin structure and in contact with the recessed surface of the end portions of the plurality of semiconductor layers, wherein the S/D structure extends into the end portions of the plurality of semiconductor layers.
A semiconductor device, comprising:
- a fin structure on a substrate, wherein the fin structure comprises a plurality of semiconductor layers;
- a gate structure wrapped around each of the plurality of semiconductor layers;
- a spacer structure on the fin structure and in contact with sidewalls of the gate structure;
- and
- first and second S/D structures on opposite ends of the plurality of semiconductor layers, wherein the first and second S/D structures laterally extends below the spacer structure, and wherein a distance between the first and second S/D structures at a center region of the plurality of semiconductor layers is less than a length of the plurality of semiconductor layers at an edge region.
A semiconductor device, comprising:
- a plurality of semiconductor layers on a substrate, wherein:
- each of the plurality of semiconductor layers comprises a center region and an edge region;
- the center region has a first length;
- and
- the edge region has a second length greater than the first length;
- a gate structure in contact with the edge region and wrapped around the edge region of the plurality of semiconductor layers;
- and
- a source/drain (S/D) structure adjacent to end portions of the plurality of semiconductor layers, wherein the S/D structure is in contact with the center region and the end region of the plurality of semiconductor layers.
Dependencies are inferred from the claim text.