Integrated circuit structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
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Abstract
An integrated circuit (IC) structure includes a substrate and a fin structure. The substrate includes a first cell region and a second cell region abutting the first cell region. The fin structure includes a first plan-view profile within the first cell region and a second plan-view profile within the second cell region. The first plan-view profile includes a first sidewall and a second sidewall opposing the first sidewall. The second plan-view profile includes a third sidewall and a fourth sidewall opposing the third sidewall. A width between the first sidewall and the second sidewall is greater than a width between the third sidewall and the fourth sidewall.
Claims20
An integrated circuit (IC) structure, comprising:
- a substrate comprising a first cell region and a second cell region abutting the first cell region;
- and
- a fin structure comprising a first plan-view profile within the first cell region and a second plan-view profile within the second cell region, the first plan-view profile comprising a first sidewall and a second sidewall opposing the first sidewall, the second plan-view profile comprising a third sidewall and a fourth sidewall opposing the third sidewall, wherein a width between the first sidewall and the second sidewall is greater than a width between the third sidewall and the fourth sidewall.
An IC structure, comprising:
- a first transistor within a first cell region, the first transistor comprising a first channel region in a first fin, a first gate extending across the first channel region, and first source/drain epitaxial regions at opposite sides of the first gate;
- and
- a second transistor within a second cell region abutting the first cell region, the second transistor comprising a second channel region in a second fin, a second gate extending across the second channel region, and second source/drain epitaxial regions at opposite sides of the second gate, wherein the second source/drain epitaxial regions have a maximal width smaller than a maximal width of the first source/drain epitaxial regions, wherein the first fin has a longitudinal end in direct contact with a longitudinal end of the second fin.
An IC structure, comprising:
- a first transistor within a first cell region, the first transistor comprising a first channel region in a first fin, a first gate extending across the first channel region, and first source/drain epitaxial regions at opposite sides of the first gate;
- and
- a second transistor within a second cell region abutting the first cell region, the second transistor comprising a second channel region in a second fin, a second gate extending across the second channel region, and second source/drain epitaxial regions at opposite sides of the first gate, wherein the first gate comprises a work function metal different from a work function metal of the second gate, wherein the first fin and the second fin are included in a continuous fin structure having a first plan-view profile within the first cell region and a second plan-view profile within the second cell region, wherein the first plan-view profile comprises a first sidewall and a second sidewall opposing the first sidewall, the second plan-view profile comprises a third sidewall and a fourth sidewall opposing the third sidewall, wherein a width between the first sidewall and the second sidewall is greater than a width between the third sidewall and the fourth sidewall.
Dependencies are inferred from the claim text.