Semiconductor device structure and methods of forming the same

A semiconductor device structure, comprising:

• a source/drain epitaxial feature comprising a semiconductor material;
• a first semiconductor layer comprising a first channel region and a first extended source/drain region, wherein the first extended source/drain region is distinct from the source/drain epitaxial feature, wherein the first extended source/drain region is disposed between the first channel region and the semiconductor material, and the first extended source/drain region has a first width;
• and
• a second semiconductor layer disposed over the first semiconductor layer, wherein the second semiconductor layer comprises a second channel region and a second extended source/drain region, the second extended source/drain region is disposed between the second channel region and the semiconductor material, and the second extended source/drain region has a second width different from the first width.

A method, comprising:

• forming a fin comprising a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, and a third semiconductor layer disposed over the second semiconductor layer;
• removing portions of the fin to expose a substrate portion;
• depositing a first semiconductor material over the substrate portion, wherein the first semiconductor material has a first portion in contact with the first semiconductor layer, a second portion in contact with the second semiconductor layer, and a third portion in contact with the third semiconductor layer, the first portion has a first thickness, the second portion has a second thickness different from the first thickness, and the third portion has a third thickness;
• heating the first semiconductor material and the first, second, and third semiconductor layers to a temperature ranging from about 800 degrees Celsius to about 1000 degrees Celsius;
• and
• forming a gate electrode layer surrounding at least a portion of each of the first, second, and third semiconductor layer.