Semiconductor device with silicide gate fill structure

A method, comprising:

• forming an interlevel dielectric layer in an integrated circuit;
• forming a first transistor including:
• forming a first trench in the interlevel dielectric layer above a plurality of first semiconductor nanosheets co;
• depositing a first gate dielectric on a bottom and on sidewalls of the first trench;
• and
• forming a first gate electrode, including:
• depositing a first gate metal having a first material and positioned in direct physical contact with a first portion of a sidewall of the first gate dielectric in the first trench;
• depositing a second gate metal in the first trench on the first gate metal, the second gate metal having a second material different from the first material and in direct physical contact with a second portion of the sidewall of the first gate dielectric in the first trench above the first portion of the sidewall of the first gate dielectric;
• depositing a third gate metal in the first trench on the second gate metal and in direct physical contact with a third portion of the sidewall of the gate dielectric in the first trench above the second portion of the sidewall of the gate dielectric, wherein the second gate metal is between the first gate metal and the third gate metal;
• depositing a first silicide in the first trench above the second gate metal;
• and
• depositing a first conductive gate fill material positioned over the first gate metal and the first silicide in the first trench, wherein the first conductive gate fill material extends to a higher vertical level within the first trench than the first gate metal, wherein an entirety of first gate metal and an entirety of the second gate metal are below an entirety of the first silicide in the first trench, wherein the first gate metal, the second gate metal, and the third gate metal surround the first semiconductor nanosheets, wherein the third gate metal, the first silicide, and the first gate fill material extend to a same height.

A method, comprising:

• forming a plurality of first semiconductor nanosheets corresponding to channel regions of a first transistor;
• and
• forming a first gate structure of the first transistor above the first semiconductor nanosheets including:
• forming a first trench in an interlevel dielectric layer above the first semiconductor nanosheets;
• forming a first gate dielectric on a bottom of the first trench;
• forming a first gate metal in the first trench and having a first material in direct physical contact with a first portion of a sidewall of the first gate dielectric in the first trench;
• forming a second gate metal on the first gate metal in the first trench and having a second material different from the first material and in direct physical contact with a second portion of the sidewall of the first gate dielectric above the first portion of the sidewall of the first gate dielectric;
• depositing a third gate metal in the first trench on the second gate metal and in direct physical contact with a third portion of the sidewall of the first gate dielectric in the first trench above the second portion of the sidewall of the gate dielectric, wherein the second gate metal is between the first gate metal and the third gate metal;
• forming a first silicide above the second gate metal in the first trench;
• forming a first conductive gate fill material over the first gate metal and the silicide, wherein the conductive gate fill material extends to a higher vertical level within the first trench than does the first gate metal, wherein an entirety of first gate metal and an entirety of the second gate metal are below an entirety of the silicide in the first trench, wherein the first gate metal, the second gate metal, and the third gate metal surround the first semiconductor nanosheets, wherein the third gate metal, the silicide, and the gate fill material extend to a same height;
• forming a plurality of second semiconductor nanosheets corresponding to channel regions of a second transistor;
• and
• forming a second gate structure of the second transistor above the second semiconductor nanosheets including:
• forming a second trench in the interlevel dielectric layer above the second semiconductor nanosheets;
• forming a second gate dielectric in the second trench;
• forming a fourth gate metal over the second gate dielectric in the second trench;
• forming a second silicide above the fourth gate metal in the second trench;
• forming a second conductive gate fill material over the fourth gate metal and the second silicide in the second trench, wherein the second conductive gate fill material is positioned closer to the second nanosheets than the first conductive gate fill material is to the first nanosheets.